circt
hdlConvertor
Our great sponsors
| circt | hdlConvertor | |
|---|---|---|
| 6 | 1 | |
| 1,506 | 264 | |
| 3.3% | - | |
| 9.9 | 5.8 | |
| 3 days ago | 3 months ago | |
| C++ | C++ | |
| GNU General Public License v3.0 or later | MIT License |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
circt
-
Ask HN: How to get a job as a compiler engineer?
MLIR (https://mlir.llvm.org/) is a quickly growing compiler toolkit which attempts to synthesize the learnings of LLVM and currently powers compilers for programming languages, machine learning and circuit design (https://github.com/llvm/circt). and there are a ton of companies with real employees working on it (including Microsoft) and MLIR is at the core of Chris Lattner’s new company, ModularAI. I’d recommend taking a look at it, there are a large number of ways to get involved and a number of paths from contributor to employee.
-
Rapid Open Hardware Development (ROHD) Framework by Intel
Might be good to target the CIRCT infrastructure at some point.
-
TSMC eyes Germany for first European chip production plant
Even small optimizations like removing unused pins from internal modules are often times opposed.
Chris Lattner and others are currently working on an "industry" version of firrtl as part of the CIRCT hardware compiler framework: https://github.com/llvm/circt
-
Chisel/Firrtl Hardware Compiler Framework
Did you see the work being done on CIRCT? https://github.com/llvm/circt
I remember one of the reasons you did not want to use firrtl was that its compiler is implemented in Scala and thus hard to integrate into other projexts. CIRCT will solve that problem by providing a firrtl compiler implemented in C++. Other languages like Verilog/VHDL and new high level languages for HLS-like designs are also on the todo list.
- Julia Receives DARPA Award to Accelerate Electronics Simulation by 1,000x
-
VHDL backend
Relevant: https://github.com/llvm/circt
hdlConvertor
-
VHDL backend
Have you seen https://github.com/dalance/sv-parser, https://github.com/google/verible, https://github.com/alainmarcel/Surelog, https://github.com/Nic30/hdlConvertor? I think there was at least one more that I stumbled across, but can't find at the moment.
What are some alternatives?
SpinalHDL - Scala based HDL
vscode-terosHDL - VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
chisel - Chisel: A Modern Hardware Design Language
naja-verilog - A standalone structural (gate-level) verilog parser
torch-mlir - The Torch-MLIR project aims to provide first class support from the PyTorch ecosystem to the MLIR ecosystem.
rggen - Code generation tool for control and status registers
mlir-aie - An MLIR-based toolchain for AMD AI Engine-enabled devices.
verible - Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
cocotb - cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
Surelog - SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
amaranth - A modern hardware definition language and toolchain based on Python
clash-ghc - Haskell to VHDL/Verilog/SystemVerilog compiler