circt
chiselverify
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circt | chiselverify | |
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6 | 1 | |
1,513 | 130 | |
3.8% | 2.3% | |
9.9 | 2.2 | |
3 days ago | 15 days ago | |
C++ | Scala | |
GNU General Public License v3.0 or later | BSD 2-clause "Simplified" License |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
circt
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Ask HN: How to get a job as a compiler engineer?
MLIR (https://mlir.llvm.org/) is a quickly growing compiler toolkit which attempts to synthesize the learnings of LLVM and currently powers compilers for programming languages, machine learning and circuit design (https://github.com/llvm/circt). and there are a ton of companies with real employees working on it (including Microsoft) and MLIR is at the core of Chris Lattner’s new company, ModularAI. I’d recommend taking a look at it, there are a large number of ways to get involved and a number of paths from contributor to employee.
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Rapid Open Hardware Development (ROHD) Framework by Intel
Might be good to target the CIRCT infrastructure at some point.
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TSMC eyes Germany for first European chip production plant
Even small optimizations like removing unused pins from internal modules are often times opposed.
Chris Lattner and others are currently working on an "industry" version of firrtl as part of the CIRCT hardware compiler framework: https://github.com/llvm/circt
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Chisel/Firrtl Hardware Compiler Framework
Did you see the work being done on CIRCT? https://github.com/llvm/circt
I remember one of the reasons you did not want to use firrtl was that its compiler is implemented in Scala and thus hard to integrate into other projexts. CIRCT will solve that problem by providing a firrtl compiler implemented in C++. Other languages like Verilog/VHDL and new high level languages for HLS-like designs are also on the todo list.
- Julia Receives DARPA Award to Accelerate Electronics Simulation by 1,000x
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VHDL backend
Relevant: https://github.com/llvm/circt
chiselverify
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Chisel/Firrtl Hardware Compiler Framework
Chisel is not HLS. It is a Scala library that lets you generate circuits on an RTL abstraction level. That means that you explicitly define every state element like registers and memories. But you can generate N registers inside a loop (or a map/foreach) instead of only 1 at a time. In HLS the compiler needs to somehow infer your registers and memories.
That said, I think one of the problems the google team was struggling with is that in traditional HW development there is design and a separate verification team. The design team bought into Chisel since it would let them generate hardware more quickly, but the verification team just tried to apply their traditional verification methods on the _generated_ Verilog. This is almost like trying to test the assembly that a C++ compiler generates instead of trying to test the C++ program since all your testing infrastructure is setup for testing assembly code and that is "what we have always been doing".
In order to catch verification up to modern Hardware Construction Languages [0] we need more powerful verification libraries that can allow us to build tests that can automatically adapt to the parameters that were supplied to the hardware generator. There are different groups working on this right now. The jury is still out on how to best solver the "verification gap". In case you are interested:
- https://github.com/chiselverify/chiselverify
What are some alternatives?
SpinalHDL - Scala based HDL
chisel - Chisel: A Modern Hardware Design Language
cocotb - cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
hdlConvertor - Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
amaranth - A modern hardware definition language and toolchain based on Python
torch-mlir - The Torch-MLIR project aims to provide first class support from the PyTorch ecosystem to the MLIR ecosystem.
mlir-aie - An MLIR-based toolchain for AMD AI Engine-enabled devices.
chiseltest - The batteries-included testing and formal verification library for Chisel-based RTL designs.
fault - A Python package for testing hardware (part of the magma ecosystem)