boxlambda
vscode-terosHDL
| boxlambda | vscode-terosHDL | |
|---|---|---|
| 1 | 3 | |
| 45 | 574 | |
| - | 3.5% | |
| 8.8 | 9.1 | |
| 18 days ago | about 1 month ago | |
| VHDL | VHDL | |
| MIT License | GNU General Public License v3.0 only |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
boxlambda
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BoxLambda DevLog: Hello Debugger!
BoxLambda is a Blog and an open-source project with the goal of creating a retro-style FPGA-based microcomputer. The microcomputer serves as a platform for software and RTL experimentation.
vscode-terosHDL
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Sigasi's price
You can try TerosHDL: https://terostechnology.github.io/terosHDLdoc/
- (System)Verilog Linting in VSCode?
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sublime System Verilog vs TerosHDL VS Code vs Synopsys Euclide
Please, open an issue in: https://github.com/TerosTechnology/vscode-terosHDL
What are some alternatives?
jtbin - Binary files for MiSTerFPGA, Pocket and other platforms
hdl_checker - Repurposing existing HDL tools to help writing better code
rggen - Code generation tool for control and status registers
oss-cad-suite-build - Multi-platform nightly builds of open source digital design and verification tools
verilog_template - A template for starting a Verilog project with FuseSoC integration, Icarus simulation, Verilator linting, Yosys usage report, and VS Code syntax highlighting.
hdlConvertor - Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
clash-ghc - Haskell to VHDL/Verilog/SystemVerilog compiler
edalize - An abstraction library for interfacing EDA tools
pyxhdl - Python Frontend For VHDL And Verilog
spi-to-axi-bridge - An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
Compliance-Tests - Tests to evaluate the support of VHDL 2008 and VHDL 2019 features
Innervator - Innervator: Hardware Acceleration for Neural Networks