capstone
cv32e40p
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| capstone | cv32e40p | |
|---|---|---|
| 1 | 3 | |
| 5,294 | 869 | |
| - | 2.0% | |
| 5.3 | 9.1 | |
| over 2 years ago | 5 days ago | |
| C | SystemVerilog | |
| GNU General Public License v3.0 or later | GNU General Public License v3.0 or later |
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For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
capstone
cv32e40p
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ALU CIRCUIT DESIGN LEVEL VS RTL LEVEL
For a high performance CPU I would expect the second approach, eventually using RTL only to connect the single blocks like adders, shifters, comparators etc... but looking at some projects available on GitHub (for example Pulp RISC-V CPU https://github.com/openhwgroup/cv32e40p/blob/master/rtl/cv32e40p_alu.sv) the ALU is always fully coded in RTL.
- Are FPGAs the best choice for this project?
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2 questions after finishing digital logic
Here is an example of a GitHub repository for a riscv core I found on google: https://github.com/openhwgroup/cv32e40p/tree/master/rtl
What are some alternatives?
Unicorn Engine - Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, S390x, TriCore, X86)
cva6 - The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
radare2 - UNIX-like reverse engineering framework and command-line toolset
riscv-simple-sv - A simple RISC V core for teaching
zydis - Fast and lightweight x86/x86-64 disassembler and code generation library
Cores-VeeR-EL2 - VeeR EL2 Core
ret-sync - ret-sync is a set of plugins that helps to synchronize a debugging session (WinDbg/GDB/LLDB/OllyDbg2/x64dbg) with IDA/Ghidra/Binary Ninja disassemblers.
Cores-VeeR-EH1 - VeeR EH1 core
android-inline-hook - :fire: ShadowHook is an Android inline hook library which supports thumb, arm32 and arm64.
friscv - RISCV CPU implementation in SystemVerilog
reko - Reko is a binary decompiler.
vgm_ripping - Sources for game music ripping tools