antikernel
The Antikernel operating system project (by azonenberg)
PipelineC
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature. (by JulianKemmerer)
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| antikernel | PipelineC | |
|---|---|---|
| 2 | 46 | |
| 110 | 541 | |
| - | - | |
| 0.0 | 9.4 | |
| about 4 years ago | 6 days ago | |
| Verilog | Python | |
| - | GNU General Public License v3.0 only |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
antikernel
Posts with mentions or reviews of antikernel.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-07-14.
PipelineC
Posts with mentions or reviews of PipelineC.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2024-03-03.
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PipelineC Example: FM Radio Demodulation (FPGA SDR)
Related: PipelineC: A C-like hardware description language (HDL):
https://github.com/JulianKemmerer/PipelineC
- Generate non-CPU FPGA circuits from a C-like language
- What makes C, Verilog, Java, Python, etc. so different?
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What are your private FPGA projects and why?
https://github.com/JulianKemmerer/PipelineC :)
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What's the right path to learning for someone coming from software?
However, I think its still possible to have a productive C->HDL journey. Check out PipelineC, https://github.com/JulianKemmerer/PipelineC, its meant for folks with C experience to get right into doing RTL style reasoning :)
- Seeking Advice on How to approch RTL Programming
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Using FPGAs for computations as a beginner
https://github.com/JulianKemmerer/PipelineC-Graphics/blob/main/doc/Sphery-vs-Shapes.pdf https://github.com/JulianKemmerer/PipelineC
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Generating pipeline stages automatically?
This is exactly what the PipelineC tool was made for. https://github.com/JulianKemmerer/PipelineC
- Does Xilinx use multiplication algorithms to speed up/reduce the multipliers size?
- Sphery vs. Shapes, the first raytraced game that is not software
What are some alternatives?
When comparing antikernel and PipelineC you can also consider the following projects:
OpenCL-ICD-Loader - The OpenCL ICD Loader project.
pygears - HW Design: A Functional Approach
optimus-hypervisor
cocotb - cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
opencpi - Open Component Portability Infrastructure
pycparser - :snake: Complete C99 parser in pure Python
OpenFPGA - An Open-source FPGA IP Generator
nngen - NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network
BORPH - Operating System Extensions for Reconfigurable Computers
hls4ml - Machine learning on FPGAs using HLS
aws-fpga - Official repository of the AWS EC2 FPGA Hardware and Software Development Kit
bsc - Bluespec Compiler (BSC)