vISA
By gitlab-VitalMixofNutrients
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| VexRiscvBPluginGenerator | vISA | |
|---|---|---|
| 1 | 19 | |
| 14 | - | |
| - | - | |
| 0.0 | - | |
| over 1 year ago | - | |
| C | ||
| MIT License | - |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
VexRiscvBPluginGenerator
Posts with mentions or reviews of VexRiscvBPluginGenerator.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-09-15.
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What is your take on ISA architectures for FPGAs (x86, arm, risc-v)?
I'd say beyond availability, the primary advantage for embedded use it the adaptability of the ISA. If you just need a small microcontroller, the core can be very small; if you need some specific performance point, you can use a bigger core, some extensions (or part thereof) could help, and you can always roll your own instructions in the 'custom' opcode space to reach your goals.
vISA
Posts with mentions or reviews of vISA.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-09-27.
- My Six Lines of Verilog Code Turing Complete BitBitJump Is Now Under the GPLv3
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1-bit CPU for 'super low-performance computer' launched – sells out promptly
Speed test against my six lines of verilog cpu when? *
https://gitlab.com/VitalMixofNutrients/vISA
* Only six lines of verilog if one only uses FPGA LUTs as Ram.
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Hey I'm genuinely curious about what makes you guys like working.
Well, I made a CPU Instruction Set Architecture called Bit-Bit-Jump that can simulate Bit-Bit-Jump Machine Code at approximately 5.6 Megahertz here: https://gitlab.com/VitalMixofNutrients/vISA
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What is easier for programmers to understand? An entire program that was written in one source code file, or an entire directory of source code files getting statically / dynamically linked into an entire program?
Hello. Over the past six months, I have been working on a CPU ISA named Bit-Bit-Jump. Suprisingly, it is actually the world's simplest CPU ISA, comprising only SIX lines of Verilog code.
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Error: Unsupported tristate construct (not in propagation graph):
You're right, it doesn't look like an actual binary.. How can I turn it into an actual binary?
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What is your take on ISA architectures for FPGAs (x86, arm, risc-v)?
Well, the simplest ISA is six lines of Verilog and it's called Bit-Bit-Jump
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MSc thesis topic advice related with fpga.
Idea: Because I don't have the money for Vivado (Free version is limited to a few thousand lines of Verilog) / Quartus (Free version won't let me perform DPR), it would be awesome if you could find a way to implement my Bit-Bit-Jump Soft-Core into your project. Here's my project: https://gitlab.com/VitalMixofNutrients/vISA (Licensed under GPLv2 Only.)
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When you implement an CPU ISA (Bit-Bit-Jump) in only six lines of Verilog:
My BBJ code is available here: https://gitlab.com/VitalMixofNutrients/vISA/-/raw/vISA/sources/sim/verilator/BBJ/BBJ.v (Licensed under GPLv2 only.)
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What architecture is the most chad?
Bit-Bit-Jump.
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Anon can't get a job
(My coding project in question: https://gitlab.com/VitalMixofNutrients/vISA)
What are some alternatives?
When comparing VexRiscvBPluginGenerator and vISA you can also consider the following projects:
microwatt - A tiny Open POWER ISA softcore written in VHDL 2008
ao486_MiSTer - ao486 port for MiSTer
verilator - Fork of Verilator with prebuilt Ubuntu binaries (https://www.veripool.org/wiki/verilator)
Smallpond - Brand new RISC architecture created in CSE 490
dcc - Dan's C compiler
beri - The BERI and CHERI processor and hardware platform
MultiCPU_Microprocessor - This was the final project for CS-401 Computer Architecture. The microprocessor was built using VHDL in Xilinx Vivado. My group decided to build something akin to a GPU that could do many simple calculations simultaneously.