VexRiscv
Rudi-RV32I
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VexRiscv | Rudi-RV32I | |
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21 | 7 | |
2,214 | 105 | |
2.8% | - | |
7.6 | 0.0 | |
3 days ago | over 3 years ago | |
Assembly | VHDL | |
MIT License | MIT License |
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VexRiscv
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Need help to build a RISC-V Processor on Artix-7 FPGA: Final Year Engineering Project Guide
With LiteX you can synthesize a VexRiscV processor. You can run Linux on it. The toolchain is pretty easy to use, as long as you use Xilinx Vivado to compile to gateware.
- RISC-V with AXI Peripheral
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Intel discontinues Nios II IP
I don't get what's going on with licensing and device support. I'm missing something here perhaps, but we use Cyclone 10 GX onwards and Quartus Pro so I don't have enough context maybe. Have you considered swapping your Nios ii to a VexRISCV as a side note? At ~1 Dhrystone MIPS/MHz it's roughly double that of the Nios V, for very few resources. All open source too. None of the migration documentation support though, so I can't judge how hard it would be.
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How Much Would It Cost For A Truly Open Source RISC-V SOC?
If you use LiteX to generate a VexRiscV system-on-a-chip, you can include an open source DDR DRAM PHY. This works on Xilinx Spartan-6, Spartan7Artix7/Kintex7/Virtex7 FPGAs, and Lattice ECP5 FPGAs. DDR/LPDDR/DDR2/DDR3 depending on the FPGA.
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Which FPGA for getting into RISC-V?
Something like https://github.com/SpinalHDL/VexRiscv will take far fewer
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Looking for a suitable open-source RISC-V for an embedded project
4) https://github.com/SpinalHDL/VexRiscv
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What do think of Chisel HDL? is it worth learning over Verilog/SystemVerilog?
I really like Chisel HDL or any other new HDL languages like SpinalHDL or migen b/c it allows you to create some very complex yet modular designs. See VexRiscv or LiteX for instance. Languages like this exist b/c there is a need for it, but I wouldn't say that you should learn these new languages over verilog. All these languages output verilog/VHDL for now, but there is work being to done eliminate the need for outputting verilog; eventually, Chisel will output an open source CIRCT IR. Hope is to get EDA vendors to support this IR which I'm sure will take a while. For now, you should definitely learn Verilog or VHDL before Chisel.
- Looking for help with RISC-V softcore and VHDL
- Are there any dual-GBE, PoE-capable SBCs?
- Tips on building a RISC-V processor on FPGA
Rudi-RV32I
- Running Hello World on a bare-metal RISC-V FPGA
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CPU DESIGN
Here was my first attempt at a RV32I design, https://github.com/hamsternz/Rudi-RV32I
What are some alternatives?
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
ibex - Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
RISCV-FiveStage - Marginally better than redstone
wb2axip - Bus bridges and other odds and ends
darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
sdspi - SD-Card controller, using a SPI interface that is (optionally) shared
dromajo - RISC-V RV64GC emulator designed for RTL co-simulation
riscv-tests
scr1 - SCR1 is a high-quality open-source RISC-V MCU core in Verilog
riscv_vhdl - Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
litex - Build your hardware, easily!