Pyverilog
pyverilator
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| Pyverilog | pyverilator | |
|---|---|---|
| 2 | 1 | |
| 571 | 70 | |
| 3.7% | - | |
| 0.0 | 0.0 | |
| 9 months ago | 2 months ago | |
| Python | Python | |
| Apache License 2.0 | MIT License |
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For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Pyverilog
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Tools for designing hardware in Python
Any hardware designers here who use Python for designing hardware? There are a bunch of libraries that all seem promising MyHDL, PyRTL, PyVerilog, PyLog, PyMTL3, ... All seem to work roughly the same. Write code in Python and transpile it to VHDL/Verilog. Which of these are popular and well-maintained? MyHDL looks good but it's last release was 0.10 in 2018 and for hardware design you don't want to rely on 0.x software. Anything like Chisel for Python.
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How to compare HDL simulation/implementation results to Matlab?
PyVerilog https://github.com/PyHDI/Pyverilog
pyverilator
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How to compare HDL simulation/implementation results to Matlab?
I'd use something I could drive from Python, like https://github.com/csail-csg/pyverilator and verilator since it is fast. I'd containerize the tests and use [py.test]https://docs.pytest.org/en/6.2.x/) to run specific unit or integration tests. Ideally everything would be parameterized.
What are some alternatives?
myhdl - The MyHDL development repository
nmigen - A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen
PyRTL - A collection of classes providing simple hardware specification, simulation, tracing, and testing suitable for teaching and research. Simplicity, usability, clarity, and extendability rather than performance or optimization is the overarching goal.
qemu - Xilinx's fork of Quick EMUlator (QEMU) with improved support and modelling for the Xilinx platforms.
datamodel-code-generator - Pydantic model and dataclasses.dataclass generator for easy conversion of JSON, OpenAPI, JSON Schema, and YAML data sources.
axi - AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
nngen - NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network
pymtl3 - Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
pylog - PyLog: An Algorithm-Centric FPGA Programming and Synthesis Flow