Pyverilog
nmigen
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| Pyverilog | nmigen | |
|---|---|---|
| 2 | 3 | |
| 571 | 643 | |
| 3.7% | 1.2% | |
| 0.0 | 1.8 | |
| 9 months ago | over 2 years ago | |
| Python | Python | |
| Apache License 2.0 | GNU General Public License v3.0 or later |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Pyverilog
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Tools for designing hardware in Python
Any hardware designers here who use Python for designing hardware? There are a bunch of libraries that all seem promising MyHDL, PyRTL, PyVerilog, PyLog, PyMTL3, ... All seem to work roughly the same. Write code in Python and transpile it to VHDL/Verilog. Which of these are popular and well-maintained? MyHDL looks good but it's last release was 0.10 in 2018 and for hardware design you don't want to rely on 0.x software. Anything like Chisel for Python.
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How to compare HDL simulation/implementation results to Matlab?
PyVerilog https://github.com/PyHDI/Pyverilog
nmigen
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Help a newbie
You can either decide to learn VHDL/Verilog, or use something like nmigen. I recommend learning either Verilog or VHDL anyway, so you can at least read and understand existing designs, but I personally use nmigen.
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Do these work as JTAG programmers?
Alternatively, you can just use Vivado to build the bitstream and then use alternative tools like https://github.com/trabucayre/openFPGALoader and http://xc3sprog.sourceforge.net/ to upload the bitstream to your FPGA. This is what I do since I use nmigen myself.
- How to compare HDL simulation/implementation results to Matlab?
What are some alternatives?
pyverilator - Python wrapper for verilator model
myhdl - The MyHDL development repository
PyRTL - A collection of classes providing simple hardware specification, simulation, tracing, and testing suitable for teaching and research. Simplicity, usability, clarity, and extendability rather than performance or optimization is the overarching goal.
axi - AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
datamodel-code-generator - Pydantic model and dataclasses.dataclass generator for easy conversion of JSON, OpenAPI, JSON Schema, and YAML data sources.
openFPGALoader - Universal utility for programming FPGA
nngen - NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network
XVC-FTDI-JTAG - Xilinx virtual cable server for generic FTDI 4232H.
pymtl3 - Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
xvcd - Xilinx Virtual Cable Daemon