OsvvmLibraries VS Documentation

Compare OsvvmLibraries vs Documentation and see what are their differences.

OsvvmLibraries

Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script. (by OSVVM)

Documentation

OSVVM Documentation (by OSVVM)
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OsvvmLibraries Documentation
2 1
45 27
- -
7.9 5.2
5 days ago about 1 month ago
QMake
GNU General Public License v3.0 or later -
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

OsvvmLibraries

Posts with mentions or reviews of OsvvmLibraries. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-02-02.

Documentation

Posts with mentions or reviews of Documentation. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2021-12-04.
  • Comments and rants about tools, and a crazy idea
    3 projects | /r/FPGA | 4 Dec 2021
    The OSVVM API runs on Siemen's ModelSim/QuestaSim, Aldec's Active-HDL/Riviera-PRO, GHDL (open source), Synopsys' VCS and Cadence's Xcelium. The advantage of this is that there is one API to run any of them. It is a work in progress. We are open source and accept contributions. We have a start at running XSIM, but are not focused on that as XSIM does not yet support the OSVVM verification utility libraries (2021.1). My blog on the scripting is at: https://osvvm.org/archives/1876All documentation is here: https://github.com/OSVVM/Documentation/tree/master

What are some alternatives?

When comparing OsvvmLibraries and Documentation you can also consider the following projects:

cocotb - cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

vunit - VUnit is a unit testing framework for VHDL/SystemVerilog

viv-prj-gen - tcl scripts used to build or generate vivado projects automatically

AXI4 - AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components