hardware
Verilog development and verification project for HOL4 (by CakeML)
vericert
A formally verified high-level synthesis tool based on CompCert and written in Coq. (by ymherklotz)
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| hardware | vericert | |
|---|---|---|
| 2 | 1 | |
| 23 | 80 | |
| - | - | |
| 0.0 | 8.3 | |
| about 1 year ago | about 1 month ago | |
| Standard ML | Coq | |
| BSD 3-clause "New" or "Revised" License | GNU General Public License v3.0 only |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
hardware
Posts with mentions or reviews of hardware.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-12-03.
-
There's an ongoing effort to rewrite Principia Mathematica using Coq
There are ongoing research projects about that, you may want to have a look at Kôika (https://github.com/mit-plv/koika), Kami (https://github.com/mit-plv/kami), Lutsig (https://github.com/CakeML/hardware) and silveroak (https://github.com/project-oak/silveroak). Closer to HLS there is also Vericert (https://github.com/ymherklotz/vericert). There may be other research project I am unaware of, feel free to add them in a reply, I am interested in it.
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Lutsig - A verified Verilog synthesizer
All source code and proofs are available on Github: https://github.com/CakeML/hardware. However, if you are not familiar with the HOL4 theorem prover it's not entirely straightforward to run Lutsig since you currently have to run Lutsig inside the theorem prover.
vericert
Posts with mentions or reviews of vericert.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-12-03.
-
There's an ongoing effort to rewrite Principia Mathematica using Coq
There are ongoing research projects about that, you may want to have a look at Kôika (https://github.com/mit-plv/koika), Kami (https://github.com/mit-plv/kami), Lutsig (https://github.com/CakeML/hardware) and silveroak (https://github.com/project-oak/silveroak). Closer to HLS there is also Vericert (https://github.com/ymherklotz/vericert). There may be other research project I am unaware of, feel free to add them in a reply, I am interested in it.
What are some alternatives?
When comparing hardware and vericert you can also consider the following projects:
NyuziProcessor - GPGPU microprocessor architecture
koika - A core language for rule-based hardware design 🦑
cakeml - CakeML: A Verified Implementation of ML
CompCert - The CompCert formally-verified C compiler
silveroak - Formal specification and verification of hardware, especially for security and privacy.
kami - A Platform for High-Level Parametric Hardware Specification and its Modular Verification
ConCert - A framework for smart contract verification in Coq
Doubly-Linked-List-VST - The final project for CS2603 (2021 Spring), aiming to verify a doubly linked list library using VST. Collaborating with @karzexcc